1. Field of the Invention
The invention relates to a process for an integrated circuit package that contains a flexible circuit board.
2. Background of the Information
Integrated circuits (IC""s) are typically assembled into a package that is mounted to a printed circuit board. The printed circuit board may be, for example, the motherboard of a computer. The IC may be mounted to a substrate or interposer and encapsulated with a plastic or epoxy material. A process known to those skilled in the art as flip-chip technology may be used to attach an IC to a substrate with the IC""s I/O (input/output) side facing the substrate. One method that may be. used to attach the flip-chip to the substrate is known as C4 (controlled-collapse chip connection) attachment. With C4, solder bumps are placed on metal terminals on the chip and a matching area of solder terminals on the substrate. The chip is then aligned to the substrate, and all solder connections are made simultaneously by reflowing the solder. The substrate is typically a printed circuit board (PCB) that has a number of pins, known as pin grid array (PGA), or solder balls, known as a ball grid array (BGA), that can be connected to a motherboard.
A substrate such as a PCB typically contains a number of routing traces, vias and solder pads that electrically connect the integrated circuit to the motherboard. The routing traces and solder pads may be separated by one or more layers of dielectric material.
The substrate/printed circuit board is fabricated before the integrated circuit is mounted to the substrate. The substrate must be thick enough to provide enough structural integrity to support the integrated circuit during the mounting process.
For CMOS (complementary metal oxide semiconductor) logic applications, the integration of an IC chip into a single package is typically accomplished through a multi-chip module using a two-dimensional array. This type of package, however, suffers from longer inter-chip connection length. Some of the problems arising from such a package are high propagation delay, high inductance, and cross-talking noise. In a case where a three-dimensional array integration package is used, chips are stacked on top of each other and the inter-chip interconnection is achieved through edge wire bonding. A problem with this type of package is that the total I/O is limited.
In an array interconnect package, alignment and attachment are typically difficult to accomplish. For de-coupling needs, discrete de-coupling capacitors are typically mounted on the die-side or land-side of the package after die attachment. For die-side capacitors, a larger package is typically required which increases cost. For land-side capacitors, a typical package has a large die-to-capacitor separation and a large current loop, which leads to large inductance and degraded system performance.
Because of the limitation in making high performance and fine pitch wiring on an IC board, however, the power signal wire on the IC board are not dense enough to connect directly to the contact bumps concentrated in a small chip area. A redistribution layer, i.e. interposer layer, needs to be inserted between the chip and the PC board to provide pitch adjustment and connection routing. Such an interposer layer is used only to solve what is called an xe2x80x9cescape problemxe2x80x9d in flip-chip mounting. Therefore the interposer layer functions only in a passive mode. The only function of the passive interposer, therefore, is to provide more efficient and fast signal/clock routing and power distribution. Presently, organic land grid array substrates or flexible circuitry substrates are used as a passive interposer layer which, provides an interconnect function between the IC chip and the IC board.